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<div class="header">
  <div class="headertitle"><div class="title">DMA2D_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>DMA2D Controller.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:afb0ef686f69afae3e9614a9b30558dcf" id="r_afb0ef686f69afae3e9614a9b30558dcf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#afb0ef686f69afae3e9614a9b30558dcf">CR</a></td></tr>
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<tr class="memitem:a996362d8114c5c841da6c763b0df3df1" id="r_a996362d8114c5c841da6c763b0df3df1"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a996362d8114c5c841da6c763b0df3df1">RESERVED</a> [236]</td></tr>
<tr class="memitem:a4f8c1dc3470960b18ec9e3c358d0b0ad" id="r_a4f8c1dc3470960b18ec9e3c358d0b0ad"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a4f8c1dc3470960b18ec9e3c358d0b0ad">FGCLUT</a> [256]</td></tr>
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</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>DMA2D Controller. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a5e5f5a73a2c943723044960897daccc3" name="a5e5f5a73a2c943723044960897daccc3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5e5f5a73a2c943723044960897daccc3">&#9670;&#160;</a></span>AMTCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::AMTCR</td>
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</div><div class="memdoc">
<p>DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C </p>

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<a id="a2ee6a30b394faf8442becbfa8b737413" name="a2ee6a30b394faf8442becbfa8b737413"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2ee6a30b394faf8442becbfa8b737413">&#9670;&#160;</a></span>BGCLUT</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::BGCLUT[256]</td>
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</div><div class="memdoc">
<p>DMA2D Background CLUT, Address offset:800-BFF </p>

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<a id="a7b6a846a09e204c29664759983853ec0" name="a7b6a846a09e204c29664759983853ec0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7b6a846a09e204c29664759983853ec0">&#9670;&#160;</a></span>BGCMAR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::BGCMAR</td>
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</div><div class="memdoc">
<p>DMA2D Background CLUT Memory Address Register, Address offset: 0x30 </p>

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<a id="a9dad401dfd995251a189d457bc6a5ebd" name="a9dad401dfd995251a189d457bc6a5ebd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9dad401dfd995251a189d457bc6a5ebd">&#9670;&#160;</a></span>BGCOLR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::BGCOLR</td>
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</div><div class="memdoc">
<p>DMA2D Background Color Register, Address offset: 0x28 </p>

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<a id="a9d9d6051b0db4c369c7aa77c0c8740d0" name="a9d9d6051b0db4c369c7aa77c0c8740d0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9d9d6051b0db4c369c7aa77c0c8740d0">&#9670;&#160;</a></span>BGMAR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::BGMAR</td>
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<p>DMA2D Background Memory Address Register, Address offset: 0x14 </p>

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<a id="a93ae9fddd0bab5c8938015a540e6371e" name="a93ae9fddd0bab5c8938015a540e6371e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a93ae9fddd0bab5c8938015a540e6371e">&#9670;&#160;</a></span>BGOR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::BGOR</td>
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<p>DMA2D Background Offset Register, Address offset: 0x18 </p>

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<a id="a2469616cbbe6a9e9afa1b943f326add0" name="a2469616cbbe6a9e9afa1b943f326add0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2469616cbbe6a9e9afa1b943f326add0">&#9670;&#160;</a></span>BGPFCCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::BGPFCCR</td>
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<p>DMA2D Background PFC Control Register, Address offset: 0x24 </p>

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<a id="afb0ef686f69afae3e9614a9b30558dcf" name="afb0ef686f69afae3e9614a9b30558dcf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afb0ef686f69afae3e9614a9b30558dcf">&#9670;&#160;</a></span>CR</h2>

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<p>DMA2D Control Register, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4f8c1dc3470960b18ec9e3c358d0b0ad">&#9670;&#160;</a></span>FGCLUT</h2>

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<p>DMA2D Foreground CLUT, Address offset:400-7FF </p>

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<h2 class="memtitle"><span class="permalink"><a href="#afdbd6e3f06436d655b464e1ea804ea31">&#9670;&#160;</a></span>FGCMAR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t DMA2D_TypeDef::FGCMAR</td>
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<p>DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C </p>

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<p>DMA2D Foreground Color Register, Address offset: 0x20 </p>

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<p>DMA2D Foreground Memory Address Register, Address offset: 0x0C </p>

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<p>DMA2D Foreground Offset Register, Address offset: 0x10 </p>

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<p>DMA2D Foreground PFC Control Register, Address offset: 0x1C </p>

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<p>DMA2D Interrupt Flag Clear Register, Address offset: 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a03ffbd962bae5def253311b5b385cd07">&#9670;&#160;</a></span>ISR</h2>

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<p>DMA2D Interrupt Status Register, Address offset: 0x04 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa78b34a419d5a35c5504f1818ef9f122">&#9670;&#160;</a></span>LWR</h2>

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<p>DMA2D Line Watermark Register, Address offset: 0x48 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a96a187a30051332f029676b6ecd36167">&#9670;&#160;</a></span>NLR</h2>

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<p>DMA2D Number of Line Register, Address offset: 0x44 </p>

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<p>DMA2D Output Color Register, Address offset: 0x38 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4ecac7187f1a8fcd108b14abdfb4934d">&#9670;&#160;</a></span>OMAR</h2>

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<p>DMA2D Output Memory Address Register, Address offset: 0x3C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a118208b8645815a2aa670e92d6277199">&#9670;&#160;</a></span>OOR</h2>

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<p>DMA2D Output Offset Register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a50f9ee49cd295305a56ac58b96d11ded">&#9670;&#160;</a></span>OPFCCR</h2>

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<p>DMA2D Output PFC Control Register, Address offset: 0x34 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a996362d8114c5c841da6c763b0df3df1">&#9670;&#160;</a></span>RESERVED</h2>

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<p>Reserved, 0x50-0x3FF </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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